求助，有几句话翻译不出来！急！
原文Mixed-Signal Modeling with Vanilla VHDL and Verilog
Steve Watkins and Kam Wong, Blue Pacific Computing
Abstract:
This paper compares and contrasts mixed-signal modeling using hardware description languages with and without the analog and mixed-signal extensions. We argue that there are several major advantages to performing mixed-signal modeling using VHDL and Verilog without the AMS extensions. We refer to this style of modeling as vanilla HDL mixed-signal modeling. Examples of vanilla mixed-signal codec models for both VHDL and Verilog are presented.
Introduction
Designers have been fighting the problem of modeling analog and digital mixed-signal systems for years. As we are entering into the system-on-chip (SOC) integrated circuits era, the problem has become more difficult due to the larger number of transistors [1,2]. The latest weapons in this fight are the analog and mixed-signal (AMS) extensions to the VHDL and Verilog* hardware description languages (HDL's). However, these AMS extensions bring some problems with them, which prompted us to ask: "How well can mixed-signal modeling be performed without the AMS extensions?" The answer is: "Well enough to make this our preferred methodology."
Some History
In the past, designers have used a variety of simulation methodologies to verify designs that contained both analog and digital circuits. At the very highest levels of abstraction, system designers have used C/C++ and Matlab* to model systems that would be implemented with analog and digital circuits; but this approach usually doesn't try to represent any implementation issues. At the next level down in the hierarchy, designers have used Saber* by Analogy and similar tools to model mixed-signal systems. At the lowest level of abstraction, designers have modeled all the analog and digital circuits at the transistor level and used Spice-like simulators, or reduced-complexity transistor-level simulators.
Designers are just beginning to use the VHDL and Verilog AMS languages, and this approach fits somewhere in the middle compared to the above levels. The AMS extensions allow a designer to use VHDL or Verilog to describe analog circuits at different levels of abstraction, ranging from behavioral to structural. The AMS description is usually then translated to a netlist and simulated with a Spice-like simulator.
Another approach offered by major CAD companies is to provide a simulation environment that allows the user to choose from different levels of abstraction for a given simulation. Digital blocks are represented with an HDL and simulated with an HDL simulator, analog blocks are represented with transistors or an AMS HDL and simulated with a Spice-like simulator. A software backplane allows the HDL and Spice simulators to communicate via interprocess communication.
Typically lower levels of abstraction translate to slower simulation time. Consequently, simulating large mixed-signal designs solely at the transistor level with a standard Spice-like simulator may not be practical. The benefits of Spice simulation tools are that they provide the most detailed level of modeling and analysis including: DC, transient, small signal AC, filters (LaPlace and zero/pole). The costs of Spice simulation are often long simulation times and tedious design entry.
The Benefits of AMS HDL Mixed-Signal Modeling
The analog and mixed-signal (AMS) extensions for VHDL and Verilog offer a new approach to mixed-signal modeling and simulation [3,4]. They extend the syntax and the semantics of vanilla VHDL and Verilog to allow these HDL抯 to describe any type of analog behavior (including mechanical systems). See the Verilog AMS example of a digital-to-analog converter at the end of this paper.
The AMS extensions provide the means to perform behavioral mixed-signal modeling as compared to transistor-level Spice modeling, and this allows circuits to be represented at a higher level of abstraction [5]. The consequences of AMS behavioral modeling are faster simulation times and faster creation of the system earlier in the design cycle. And since AMS HDL models are usually simulated with Spice-like simulators, all of the traditional Spice type analyses and modeling options are also available.
Other benefits of the AMS extensions are: a technology-independent representation of the analog circuits, easier exploration of tradeoffs for different analog architectures, the creation of golden simulation results which can be used for regression comparison, circuits can be modeled as ideal or non ideal with specific non linearities, support of design reuse at the flexible behavioral level [6], and support of analog circuit intellectual property (IP) by not disclosing transistor-level circuit tricks.
The Benefits of Vanilla HDL Mixed-Signal Modeling
Analog and mixed-signal circuits can also be modeled with standard VHDL and Verilog. We'll refer to this style of modeling as vanilla HDL mixed-signal modeling. This type of modeling is usually at a higher level of abstraction than AMS HDL mixed-signal modeling. The key idea is to use the standard arithmetic operators (primarily multiplication and addition), and to use standard conversion functions to map between real numbers representing voltages in the analog domain and vectors representing logic values in the digital domain. Many SOC chips need only analog-to-digital converters (A2D) and/or digital-to-analog converters (D2A), and these are extremely easy to model using vanilla VHDL and Verilog techniques.
When coding with vanilla VHDL, real numbers are used on ports to represent analog inputs and outputs; CONV_INTEGER, CONV_STD_LOGIC_VECTOR, and type casting are used for conversion functions. For Verilog, 64-bit ports are used to represent analog input and output voltages; $realtobits and $bitstoreal and simple assignments are used for conversion functions.
There are several advantages of vanilla HDL mixed-signal modeling over AMS HDL modeling. The most important advantages are:
• Faster simulation
• Complete portability to the most widely-used simulation environments [7].
The vanilla approach is faster because simple arithmetic is used to compute the analog transient simulation results, while the AMS approach requires the Spice solution of ordinary differential equations via several complex steps [8]. We have found the vanilla approach to provide a speedup in simulation time by factors ranging from 10x to 50x. For example, we simulated a 4-bit D2A converter with three different models: transistor-level Spice schematic (with 50 transistors), Verilog AMS and vanilla Verilog. The simulations times for 1 microsecond of circuit simulation were: transistor-level 3.5 seconds; Verilog AMS 3.0 seconds; vanilla Verilog 0.1 second.
The vanilla models are portable to all industry standard HDL simulators because they use only the standard HDL language, and several vanilla HDL simulators support mixed-signal behavioral simulation by providing analog waveform viewing options (Blue Pacific's BlueHDL, Modeltech and Aldec).
Other vanilla HDL modeling advantages are: no new syntax or semantics for experienced HDL designers to learn, no new simulation environments to be learned or purchased, and better GUI waveform display for a large number of signals at once. These same benefits will also apply to using C/C++ HDL's for vanilla HDL mixed-signal modeling, once they become standardized.
The vanilla HDL modeling approach also provides the same benefits as the AMS HDL modeling approach over transistor-level mixed signal modeling listed in the above section. The main disadvantages of vanilla HDL modeling compared to AMS HDL modeling are: it can't provide the Spice-like analyses (DC operating point, small signal AC), and filters are harder to model. However, Spice-like analyses have to be performed at the pure transistor level eventually anyway, and filters can still be modeled with the vanilla HDL抯 using difference equations.
Real World Examples
We've modeled sigma delta codecs, ethernet transceivers, and standalone A2D's and D2A's using these vanilla HDL modeling techniques. Also included in these circuits are analog switches, amplifiers and level shifters. We are primarily an analog IP and consulting company and this approach has allowed us to provide our customers with models that they can integrate into their SOC simulations using standard VHDL and Verilog simulators.
Conclusion
The AMS extensions to VHDL and Verilog are a good idea, particularly for SOC design. But so far they have received limited use, partly because they are relatively new and partly because they require learning new syntax and semantics and the acquisition of new simulation tools. There already exists a small group dedicated to the concept of the AMS extensions to the HDL's, and we are also very interested in this approach. However, to reach a wider group of designers, this methodology is going to have to provide more widespread standard simulation environments, and it will have to win over engineers from the three main recalcitrant groups of potential users: 1) system designers, who typically don't like VHDL or Verilog and prefer Matlab and C/C++; 2) analog designers, who typically don't like languages and prefer pictures; 3) digital designers, who typically will have to learn: analog design principles, and at least one new set of HDL syntax and semantics.
For now, we think that vanilla HDL mixed-signal modeling has some significant advantages over AMS HDL mixed-signal modeling, primarily simulation speed and universal portability of models. We have used this approach to successfully provide IP models to SOC design houses and will continue to do so for the foreseeable future.
Codec Examples
Download the VHDL and Verilog codec examples from [url]www.bluepc.com/download.html.[/url]
* Matlab is a registered trademark of the Mathworks
* Saber is a registered trademark of Analogy
* Verilog is a registered trademark of Cadence Design Systems
翻译后有问题的用绿字表示
VHDL和Verilog普通的混合信号的模拟
史蒂夫沃特金斯和锦黄，蓝太平洋电脑
摘要：
本文比较和对比，混合信号模拟使用硬件描述语言以及模拟混合信号扩展。我们认为，有几个主要优点，演示混合信号模拟使用VHDL和Verilog及美国数学学会而自行增加的新功能。我们所说的这种风格的模拟，作为普通高速硬件描述语言的混合信号模拟。不如说，普通混合信号编解码器的型号为VHDL和Verilog介绍。
导言
设计师为了模拟信号和数字混合信号争议了很多年。由于我们进入系统单晶片（ SoC ）集成电路的时代，规模较大的晶体管的数量使这个问题已变得更加困难 。最新的说法在这场争议中是模拟和混合信号（美国数学学会）扩展到VHDL和Verilog *硬件描述语言（高速硬件描述语言） 。不过，美国数学学会的扩展带来了一些问题，这促使我们问：怎么样更好的的模拟演示出美国数学学会的新功能呢？答案是： “能源的充足才是我们的最先考虑的问题” 。
一些历史
在过去，设计者采用了各种模拟方法，来验证设计，载有模拟和数字电路。在最高层次的思路里，系统设计人员使用的C / C + +和MATLAB *模型系统将实施模拟和数字电路; 但这种做法通常不会用于不代表任何完成的问题。在这个层次里技术的降低，设计师用软件工具*通过类比和类似的分析工具来模型混合信号系统。以最低的水平技术，思路，设计者为蓝本，所有的模拟和数字电路在晶体管的水平和使用的香料一样的模拟器，或减少复杂性晶体管级仿真器。
设计师只是在刚刚开始的时候，使用VHDL和Verilog美国数学学会而自行增加的新功能的语言，这种方法适用于某些地方，与中东相比，上述的技术水平就可以。美国数学学会而自行增加的新功能，让设计师使用VHDL或Verilog来形容，模拟电路，不同层次的问题，包括从行为结构。美国数学学会增加的新功能的描述通常是，然后转[color=Lime]化为一网表和模拟与红红火火一样的模拟器。[/color]
另一种方法所提供的主要的CAD公司，是要提供一个仿真环境，使用户可以选择从不同的层面思路为某一特定的模拟。数位区块的代表与一HDL和模拟与高速硬件描述模拟器，模拟区块的代表与晶体管或美国数学学会增加的新功能的高速硬件描述和模拟与[color=Lime]红红火火一样的模拟器[/color]。一个软件的[color=Lime]背板[/color]，使高速硬件描述和混合信号模拟器的结合，是通过进程间的通信来实现的。
通常较低层次的程序思路转化为模拟的时间较慢。因此，大型模拟混合信号的设计，纯粹是在晶体管的水平与一个标准的[color=Lime]香料一样[/color]的模拟器可能是不实际的。好处SPICE仿真工具是他们提供最详尽的水平建模与分析，包括：直流，瞬态，小信号交流，过滤器（拉普拉斯和零/极点） 。成本SPICE仿真往往是长期的模拟时间和繁琐的设计项目。
这样的好处，就是美国数学学会的高速硬件描述的混合信号建模
该模拟及混合信号（美国数学学会）的扩展VHDL和Verilog提供了新方法的混合信号的建模与仿真。他们[color=Lime]扩大的语法和语义香草[/color]VHDL和Verilog ，让这些告诉硬件描述语言来描述任何类型的模拟行为（包括机械系统） 。看到Verilog的美国数学学会的例子，一个数位类比转换器在本月底的文件。
美国数学学会增加的新功能提供一种手段，执行能力的混合信号建模相比，晶体管级的SPICE建模，这代表电路的思路在更高层次上。这样的结果就是美国数学学会的新功能建模能使模拟时间更快和建立该系统的较早前在设计周期。而且由于医疗辅助队的高密度脂蛋白的模式通常是[color=Lime]模拟与香料一样[/color]的模拟器，所有的传统[color=Lime]香料型分析[/color]与建模方案，也可。
其他的好处，美国数学学会增加的新功能是：一个以科技独立代表性的模拟电路，更容易探索权衡不同的模拟架构，建[color=Lime]立黄金仿真结果可用于回归比较[/color]，电路可仿照作为理想或不理想与具体的非线性，支持设计重用，在[color=Lime]灵活的行为水平[/color]，[color=Lime]并支持模拟电路知识产权（ IP ）由不披露晶体管级电路的手法[/color]。
这样的好处，超高速硬件描述的混合信号建模
模拟及混合信号电路，也可以仿照标准VHDL和Verilog 。我们将参照此类方法模拟作为高速硬件描述的混合信号建模。这种类型的建模通常是在更高层次上的思路比美国数学学会的高速硬件描述的混合信号建模。关键的思路是使用标准的算术运算符（主要是乘法和除法） ，并使用标准的转换职能，地图之间的实数代表的电压在模拟域和载体域，代表的逻辑，价值观，在数字领域。很多的SoC芯片只需要类比数位转换器（ a2d ）和/或数位类比转换器（ d2a ） ，这些都是非常容易使用的模型香草VHDL和Verilog的技巧。
当编码与香草的VHDL ，[color=Lime]实数是用在港口为代表的模拟投入和产出[/color]; conv_integer ， conv_std_logic_vector ，并键入铸造用于转换职能。为Verilog的， 64位的港口是用来代表模拟输入和输出电压元; realtobits元bitstoreal和简单的任务是用于转换职能。
有几个优势，普通高速硬件描述的混合信号建模超过美国数学学会的告诉硬件描述建模。最重要的优点是：
•更快的仿真
•完整的可携性，以最广泛使用的模拟环境[ 7 ] 。
该香草的做法是更快，因为简单的算术是用于计算模拟暂态仿真的结果，而美国数学学会的做法，需要香料的解决办法常微分方程通过几个复杂的步骤[ 8 ] 。我们已经找到了香草的做法，提供一个加速在模拟的时间因素不等，从10倍到50x 。举例来说，我们模拟一个4位d2a转换器与三种不同的模式：晶体管级的SPICE示意图（ 50晶体管） ， Verilog的AMS和香草的Verilog 。模拟时代为1微秒的电路模拟的有：晶体管级三点五秒; Verilog的医疗辅助队3.0秒;香草的Verilog 0.1秒。
该香草模式是便携式的所有业界标准的HDL模拟器，因为他们只使用标准的HDL语言，和几个香草的HDL模拟器支持混合信号行为仿真，提供模拟波形查看选项（蓝色太平洋的bluehdl ， modeltech和Aldec公司） 。
其他香草的HDL建模的优点是：没有新的语法或语义经验丰富的高速硬件描述的设计师学习，就没有新的仿真环境，[color=Lime]来吸取或购买更好地贵波形显示为大量的信号一次[/color]。这些相同的好处也将适用于用C / C + +HDL的高速硬件描述，为香草的混合信号建模，一旦他们成为规范化。
该香草的HDL建模方法，也提供同样的好处，作为美国数学学会的HDL建模方法超过晶体管级混合信号建模中列出的上述一段。主要缺点香草的HDL建模相比，美国数学学会HDL建模是：它不能提供香料一样的分析（直流操作点，小信号交流） ，和过滤器较难模型。不过，香料般的分析都必须表现在纯晶体管的水平，最终无论如何，和过滤器仍然可以仿照与香草的HDL抯利用差分方程。
真实世界的例子
我们已经为蓝本西格玛三角洲编解码器，以太网收发器，和独立a2d的和d2a的使用这些香草的HDL建模技术。也包括在这些电路的模拟开关，放大器和电平移位。我们主要是一个模拟IP及咨询公司和这种做法，也使我们能够为我们的客户提供与模式，他们可以融入他们的SoC模拟使用标准的VHDL和Verilog模拟器。
结论
美国数学学会的新方法VHDL和Verilog是一个好主意，特别是SoC设计。但到目前为止，他们已获得了有限的使用，部分是因为他们是相对较新的部分，因为它们需要学习新的语法和语义，并购置新的仿真工具。已经存在一小群，专责的概念美国数学学会扩展到高速硬件描述的，我们也非常有兴趣在这方面的做法。然而，为了达成一项更广泛的集团的设计师，这种方法是将不得不提供更广泛的标准的模拟环境，这将有战胜的工程师从三个主要顽抗群体的潜在用户： 1 ）系统设计师，[color=Lime]谁通常唐'吨一样，[/color] VHDL或Verilog和喜欢的MATLAB和C / C + + ; 2 ）模拟设计师，谁通常不喜欢语文和喜欢的图片; 3 ）数码设计师，谁通常会以了解：模拟电路设计原则，并至少有一个一套新的高密度脂蛋白的语法和语义。
现在，我们认为，普通高速硬件描述的混合信号建模有一些显着的优势，超过美国数学学会的高速硬件描述的混合信号建模，仿真，主要是速度和可携性的普遍模式。我们用这种方法成功地提供IP模式，以SOC设计房子，[color=Lime]并会继续这样做可预见的将来。 [/color]
编解码器的例子
下载VHDL和Verilog编解码器的例子，从[url]www.bluepc.com[/url] / download.html 。
* MATLAB的是一个注册商标的MathWorks公司
*军刀是一个注册商标的比喻
* Verilog的是一个注册商标的Cadence设计系统 好专业的词，帮顶 我大致看了一下，楼主似乎是用google翻译的 LZ好象在搞毕业论文啊~~也是电子类专业的吧？ 我遇到专业词汇很难翻译的时候就是利用百度，因为百度只搜索中文网页，用百度搜索英文，找到对应中文的可能性非常高 第一处绿色大概是 模拟混合信号的描述语言通常会被转换成（某种格式的）电路，并被时域电路仿真器模拟 的意思吧。太专业了。而且，google翻译得很是让人眩晕...... 哇哈哈，本来想帮lz你看看的，结果发现太长了..就看不动了..哈哈..原谅我吧..帮你顶顶好了 不是毕业设计，跟毕业有关系，非让人搞翻译。 [quote]原帖由 [i]城阙九重门[/i] 于 2008-5-10 16:19 发表 [url=http://bestxian.com/redirect.php?goto=findpost&pid=157269&ptid=15123][img]http://bestxian.com/images/common/back.gif[/img][/url]
我大致看了一下，楼主似乎是用google翻译的 [/quote]
确实是的google
[[i] 本帖最后由 幸福的少男 于 2008-5-10 18:23 编辑 [/i]] 求救啊，有专业人士没？[：85] 呵呵 我英盲啊 有专业人士，就是不知道有没有专业与英语并存的人士;lol 关系到我毕业设计的打分啊，周一就要交了。
[[i] 本帖最后由 幸福的少男 于 2008-5-10 18:53 编辑 [/i]] [quote]原帖由 [i]三木子[/i] 于 2008-5-10 16:23 发表 [url=http://bestxian.com/redirect.php?goto=findpost&pid=157271&ptid=15123][img]http://bestxian.com/images/common/back.gif[/img][/url]
LZ好象在搞毕业论文啊~~也是电子类专业的吧？ [/quote]
光电信息工程 [quote]原帖由 [i]葻莛[/i] 于 2008-5-10 18:18 发表 [url=http://bestxian.com/redirect.php?goto=findpost&pid=157392&ptid=15123][img]http://bestxian.com/images/common/back.gif[/img][/url]
有专业人士，就是不知道有没有专业与英语并存的人士;lol [/quote]
好象你就是专业人士？ 这里的AMS并不是American Mathematical Society（美国数学学会），应该作为Analog/Mixed Signal （模拟混合信号）来翻译，google出来的翻译驴唇不对马嘴，建议楼主重新组织一下吧 [quote]原帖由 [i]葻莛[/i] 于 2008-5-10 18:48 发表 [url=http://bestxian.com/redirect.php?goto=findpost&pid=157470&ptid=15123][img]http://bestxian.com/images/common/back.gif[/img][/url]
这里的AMS并不是American Mathematical Society（美国数学学会），应该作为Analog/Mixed Signal （模拟混合信号）来翻译，google出来的翻译驴唇不对马嘴，建议楼主重新组织一下吧 ... [/quote]
谢谢LS 晕哦，是很专业。。。有同班外国人冒？让他们先解释一下，什么叫spice modeling,spice type,spice like，出现很多次，好像很重要。。。术语得先知道什么意思才好翻撒。。。帮顶了。。。
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